Sr. Manager Silicon Design Engineering (amd)

Job Description

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Sr. Manager Silicon Design Engineer

THE ROLE:    

As a strategical movement for future scalability, NBIO plan to setup team in Belgrade and is looking for a team lead in Belgrade to lead a cross functional team.  He/she is responsible for managing NBIO team daily execution and operation, closely collaborating with global NBIO leads, focusing on strategy/ test plan/ project execution for PCIe and Multi-subsystem interoperability verification for AMD Client product line, as well as future expansion opportunity enablement.

THE PERSON:

Candidate will manage a cross function team with around 20 team members as projected near term growth, need to have solid DV background and more than 5 years’ team management experience, fluent spoken English and very good global communication skills in English.

KEY RESPONSIBILITIES:

Strategic team development plan creation
Talent recruiting and internal talent development
Project execution schedule definition, execution tracking and signoff
·       Global communication and alignment.

·       Team performance review and management

·       Short term global travel upon business need

PREFERRED EXPERIENCE:

Global company working experience, fluent oral English
·       Direct people management experience no less than 8 in team size

·       Good communication skills in English

·       Complex IP/ASIC/SOC design verification and validation background, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort)

·       Solid background with ASIC design verification, implementation and validation, multiple ASIC tape out experience

·       Experience in project management

·       Solid knowledge on SystemVerilog/UVM, C/C++, Verilog

·       Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)

·       Knowledge on PCIe, CXL, IOMMU is a big plus

ACADEMIC CREDENTIALS:

        MSEE with minimum of 8 years, or BSEE with minimum of 10 years’ experience in digital ASIC/SOC design verification

LOCATION:

       Belgrade, Serbia

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