Design Verification Engineer (Staff Level) (amd)

Job Description

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to look at the opportunities available to come join our team.

Design Verification Engineer (Sr./Staff Level)

THE ROLE:

JOB IS FROM: italents.netVIEW
AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, Machine Learning, APU, Server and Game consoles.
IOHUB sits in the center of all data paths, it includes 2 foundation IP (name as IOHub Core and IOMMU) and one IOHUB Subsystem. IOhub Core is the PCI “host bridge” of the system which provides decoding and routing services to PCIe etc. devices. IOMMU (I/O Memory Management Unit) is responsible for address translation and memory protection, it plays a critical role on IO virtualization technology which is widely used in mega-data center.
We are searching verification experts for IOHUB Subsystem verification and Project execution.

THE PERSON:

People who have the passion to work on leading edge technology, who have solid verification capability and communication skills will be successful in this role.
• Strong team spirit
• Drive to completion
• Fluent verbal English

KEY RESPONSIBILITIES:

• IOHUB Subsystem verification strategy and scoping
• IOHUB Subsystem test plan, DRVR implementation and verification closure
• Closely work with Design/Architecture team to develop new verification components
• Organize/attend conference call for strategy alignment, status sync up etc. with global team
• Short term global travel if needed

PREFERRED EXPERIENCE:

• Global company working experience background, fluent oral English
• Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred.
• Good knowledge of UVM/Verilog/System C/System Verilog.
• Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques.
• Experience of verification planning is an asset.
• Knowledge of Virtualization is an asset.
• Strong scripting languages (Perl, C Shell, Makefile, …) experience.
• Strong collaboration skill set

ACADEMIC CREDENTIALS:

• PhD, BSc or MSc in computer science, computer engineering, or electrical engineering

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