Sr. Staff Verification Design Engineer (Tech Lead) (amd)

Job Description

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to look at the opportunities available to come join our team.

Sr. Staff Verification Design Engineer - Tech Lead

THE ROLE: 

This is an exciting opportunity to work on Design Verification in multiple industrial protocols (PCIe/Virtualization), AMD proprietary IP blocks environment, AI (Artificial Intellgent) topologies and super high speed IO interconnects.

A successful candidate will work with architects and senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Execute a project independently with global teams to achieve pre-defined goals in time
• Understand logical design architecture and provide the analyzed data to architects for review
• Improve existing UVM test bench with advanced design verification methodology to achieve the goals of reusability, configurability, and scalability
• Bring up new design features
• Accountable for project delivery.
• Establishes and maintains AMD's technological leadership position in the AI industries
• Considered as technical leader across project and departmental boundaries and has a proven track record for sustained innovation.
• Is responsible for projects or processes of significant strategic or commercial importance and for project/program results
• Deals with problems requiring cutting edge approaches and champions innovation across the organization
• Makes technical decisions that have a significant impact on product families, go to market strategies and customer satisfaction
• Provides consultative direction with management
• Coaches and mentors experienced staff
• Represents AMD to the outside technical community, partners and vendors
• Elevating current ASIC design verification quality and the simulation efficiency to higher level

PREFERRED EXPERIENCE:

• Rich experience in constructing highly scalability, configurability and reusability DV test bench.
• More than 5+ years' experience in ASIC design/verification related field in IP, Subsystem or SOC level
• Over 5 years experiences minimum in writing System Verilog and/or System C models for simulation
• More than 5 years working experience in writing UVM models, checkers and stimulus, constructing UVM register models and applying constrained random methodology in UVM test environment and stimulus
• Compose test plan and validation vectors to ensure functional completeness
• Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
• Be versatile in any one of the high level verification flow such as SV,UVM, C++ etc. as well as knowledge of industry standard tools for verification
• Have excellent communication skills (both written and oral)
• Strong problem solving skills
• Excellent programming and scripting languages and 5+ years experience in SV, C/C++, Shell, Perl, Python, TLM2.0 

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Computer Engineering/Computer Science/Electrical Engineering

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