Lead Timing Engineer (intel)

Job Description

In Q4 2023, Intel announced Altera will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel. 
This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future.

Join Our Team: Come join Intel’s FPGA Business Unit (Altera) as a Lead Timing Engineer. We specialize in creating outstanding DDR PHYs for a wide range of applications. This unique opportunity will expose you to all phases of design development, from architecture definition to design and verification, and silicon bring-up and characterization.

What We Do: Our team works exclusively with cutting-edge, state-of-the-art technology. We focus on high-performance memories such as DDR5 and LPDDR5, and support a wide range of other interfaces including MIPI, ONFI, and older memories like DDR4 and LPDDR4.

Opportunities for Growth: There are numerous opportunities within our team to further develop your skill sets or learn something entirely new. Working for an FPGA company offers a rare chance to engage in software modeling of hardware while still working as a pure ASIC timing engineer. Additionally, our team provides exposure to mixed-signal high-speed designs, allowing you to interact with world-class analog designers. Mixed-signal design is a crucial skill set for every high-speed PHY engineer moving forward.

Key Responsibilities:

• Perform timing analysis and optimization, generate and verify timing constraints, and fix timing violations at the chip/block level for SoCs.
• Conduct timing rollups, design for functionality, and develop performance and power-optimized clock networks.
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• Develop and define methodologies to ensure the highest quality of timing models, enabling the physical design team to operate efficiently.
• Define the appropriate process, voltage, and temperature (PVT) conditions for timing analysis based on product plans such as operating conditions and binning.
• Collaborate closely with the clocking team and other backend full-chip designers for clocking balance, timing fixes, power delivery, and partitioning.
• Work with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validate high-performance, low-power clock network guidelines.

Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements:

• Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 9+ years of industry work experience
• Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6+ years of industry work experience
• PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4+ years of related work experience
• Experience in creating functional and test mode constraints for Static Timing Analysis.
• Ability to close timing for designs with multiple clock domains, resets, and power supplies.
• Experience with different styles of resets, clock gating, synchronizers, FIFOs, etc.
• Experience with industry-standard timing EDA tools.
• Experience running multi-mode, multi-corner analysis.
• Knowledge of different signal integrity requirements and methods to analyze and fix issues.
• Experience with timing and functional ECOs.
• Proven track record of closing major designs with the latest technology nodes.

Preferred Qualifications:

• Proficiency in scripting languages such as Python, Perl, or TCL.
• Experience in developing and optimizing timing models for complex digital designs.
• Expertise in creating and managing constraints for RTL synthesis.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.