Staff STA Design Automation Engineer (intel)
Job posting number: #147788 (Ref:JR0267285)
This Job Posting is Expired.
Job Description
Job Description
The Intel Programmable Solutions Group (PSG) is now Altera, an Intel Company. Altera prioritizes customers with end-to-end FPGAs, accessible AI, software, and supply resilience.
In Q4 2023, Intel announced PSG will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel. This position is associated to that standalone business strategy and will fully transition to a standalone company at some time in the future.
Specifically, you will be part of Design Methodology, Automation and Intelligence (DMAI) for Altera’s Silicon Design Engineering (SDE) group.
Designs, implements, verifies and supports enablement and adoption of Static Timing Analysis-related hardware design tools, flows, and methodologies. Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes. Develops, tests, and analyzes engineering design Static Timing Analysis-related automation tools, flows, and methodologies to improve efficiency and optimize power and performance. Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation. Builds deep understanding of digital design, verification, structural and physical layout, fullchip integration, performance, clocking, and timing to enhance future TFM development. Collaborates with EDA vendors on defining and early testing of next generation design tools.
Qualifications
BSEE/MSEE or equivalent in with minimum of 10 years experience in IC Design or Design Automation.Experience in industry Static Timing Analysis (STA), ECO and Timing Closure flow.
JOB IS FROM: italents.netVIEWThorough knowledge in concepts like Crosstalk, On-Chip-Variation is required.
Hand on experience in ASIC/SoC design flows and adjacent methodology development/support is required. Experience in advanced process 10nm and below is a plus.
Programming knowledge: primarily in Python and Tcl as well as Perl, C-shell or other software languages.
Understanding of Liberty Timing Models and their generation.
Proven leadership skills for collaborative cross-functional projects.