Digital Verification Engineer (mediatek)
mediatek HsinChu, Taiwan(China)
2024-09-07
Job posting number: #147801 (Ref:MTK120170328005)
This Job Posting is Expired.
Job Description
Description
1. To fully understand the design specification2. To identify important verification scenarios and creates test plans
3. To write test bench, monitor(s) and checker(s) by using constrained-random verification, SystemVerilog UVM, SVA, power aware simulation or formal equivalence checking
4. To identify and write all types of coverage measures; To review and increase simulation coverage
5. Setup regression environment and perform regression simulation
View Orignal JOB on: italents.net
Requirements
Familiar with Verilog languageFamiliar with Synopsys VCS
Familiar with Synopsys Verdi
Familiar with Perl/TCL/C is a plus
Familiar with SystemVerilog is a plus
Familiar with UVM is a plus
Familiar with Cadence/Synopsys AMS platform is a plus.
Familiar with Digital Design Flow is a plus.
Familiar with SerDes Design is a plus.