[2025 Internship] Physical Verification CAD Intern I (PTD/CAD) (mediatek)

Description

When you join us, you’ll work alongside with experienced engineers who’ll mentor and guide you.
You will be involved in:
• Learn design rule check coding
• Execute design rule checks on chip design and regression structures
• Study test regression structures for in house design rule
• Debug existing rule code versus regression structures
• Learn In house design checks definition methodology
• Basic scripting automation

[Learning Outcomes]
Interns will be able to
• Be familiar with linux environment
• Understand the uses of design rules to check the electrical and manufacturability of the chips
• Understand and be exposed to the process of creating new design rules
o from root cause analysis of issue, to experimental rule definition, to rule coding, to quality assurance in test regression structures
• Hands on experience with layout tool (Synopsys: Laker etc.)
• Hands on experience in design rule coding (Mentor Graphics: SVRF)
• Hands on experience executing Design rule checks (Mentor Graphics: Calibre)
• Hands on experience in scripting with tcl/python/csh
• Experience real dynamics in cross team collaboration