[2025 Internship] Physical Verification CAD Intern II (PTD/CAD) (mediatek)

Description

With guidance, you will work within CAD team to code in-house rule using Calibre Standard Verification Rule Format (SVRF). You will collaborate with process development kit team for the test pattern to verify the newly developed code, and also write script using Python to automate the run and log file processing.

You will also have a chance to integrate foundry rule release into MTK R&D environment, work with rule owner for test pattern development, rules specification and device definition and verification, or work with layout engineer to identify issue in their layout design.

[Learning Outcomes ]
• Well-verse in using Calibre SVRF for rule coding.
• Understand how devices are formed in semiconductor context.
• Expert in using Calibre for physical verification.
• Familiar with using commercial layout design tool for QA pattern generation.
• Understand the uses of physical verification flow (LVS, ERC) to check integrated circuit layout design.
• Understand the various foundry rule deck for across process technology nodes.
• Proficient in automation scripting using Python.
• Layout design LVS/ERC debugging.