[2025 Internship] NPU Physical Implementation Intern (CAI3) (mediatek)
mediatek Singapore, Singapore
2024-09-11
Job posting number: #150010 (Ref:MSL120230114008)
Job Description
Description
[What you will do]Scripting and flow automation for NPU Physical Implementation
Design one system to do data mining for all existing NPU design and Provide recommendations for later new NPU Physical Implementation best PPA recipe
View Orignal JOB on: italents.net
Requirements
[Are you the right talent?]- Bachelor’s/Master’s Degree in Electrical/Computer Engineering
Good communication and scripting skills like Python/Perl
- Knowledge in ARM/ IMG/ Tensilica Processor Familiarity, Silicon Debug and/or Functional/Direct Test Verification
- Familiar with assertion-based verification (SVA) & System Verilog language
- Knowledge in Processor verification, FPGA verification and/or Formal verification
- Familiar with Synopsys ICC (preferred) or Cadence or Magma tools from netlists to GDS is a plus
- Knowledge in graphics processor implementation/power reduction flows and methodology from RTL to GDS (including synthesis, floor-planning, placement, CTS, routing, timing optimization, physical verification) is a plus
- Knowledge of high-speed/low power IP and custom circuit design is a plus
- Familiar with power noise and reliability tools such as Redhawk and Voltus
Send us your CV our way today! Kindly add "2024 SSIA / NTU & NTU-TUM Semiconductor awareness event " as a remark.