[2025 Internship] IC Layout Engineer Intern [PTD/LO] (mediatek)
mediatek Singapore, Singapore
2024-09-11
Job posting number: #150020 (Ref:MSL120230327002)
Job Description
Description
MediaTek Layout team is looking for suitable candidates to design IC layout for Foundation and Analog/RF IP developments.[What you will do]
- Design layout for Foundation (Standard Cell) and Analog/RF IP in advance-node CMOS technologies at different hierarchies.
- Perform various physical verification checks such as Layout-versus-Schematic (LVS) and Design Rule Check (DRC) to meet circuit function, performance, and process requirements.
- Collaborate closely with IC designers and other layout engineers to meet the project specifications.
View Orignal JOB on: italents.net
Requirements
[Are you the right talent?]- Pursuing a degree in Electrical/Electronics/Materials Science Engineering
- Understands MOS and resistor’s schematic and basic layout structure.
- Strong problem solving and debugging skills
- Good communication skills, self-motivated and well-organized.
Send us your CV our way today! Kindly add "SSIA/NTU & NTU-TUM Semiconductor Awareness Event" as a remark.