Staff/Senior Staff Engineer ( Physical Design ) (mediatek)
mediatek Bangalore , India
2024-09-11
Job posting number: #150078 (Ref:MTB120240404000)
Job Description
Description
Staff/Senior Staff Engineer (physical design) – [5-10 years] M.E./M.Tech in Electronics/Electrical Engineering with minimum of 5 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level. Any leadership experience is a plus. Should have experience in 28nm & below technologies (preferably 20nm & below).• Top/Block level floor-planning, power estimation , power planning .
• Netlist and constraint sign in checks and validation .
• Design implementation environment setup .
• Netlist to GDS II implementation at IP/Block level.
• Hierarchical chip planning, block planning , block level constraint development, hierarchical clock tree implementation, block integration and chip finishing.
• Multimode multi corner optimization and closure at top level.
• Clock tree synthesis and advanced clock tree implementation at full chip level.
• Top level timing closure with sign off STA in MMMC with cross-talk and OCV .
• Top level ECO implementation strategy development for netlist ,RTL and timing level changes
• Methodology development, customization as per the specific design need.
• Good hands-on knowledge in reference flows, excellent debugging skills.
• Scripting experience in Perl/TCL.
• Flow customization and fine tuning for Power , Performance, Area.
• Strong inter-personal skills and ability to work with multiple teams.
• In depth exposure in Implementation in any of the following platforms. • FC/ICC/Innovus; Tool exposure in Sign Off • DRC/LVS : Calibre • Timing sign off : Primetime • PNA : Apache -Redhawk Job Type: Full-time Experience: • Physical Design: 10-15 years
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Requirements
Staff/Senior Staff Engineer (physical design) – [5-10 years] M.E./M.Tech in Electronics/Electrical Engineering with minimum of 5 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level. Any leadership experience is a plus. Should have experience in 28nm & below technologies (preferably 20nm & below).• Top/Block level floor-planning, power estimation , power planning .
• Netlist and constraint sign in checks and validation .
• Design implementation environment setup .
• Netlist to GDS II implementation at IP/Block level.
• Hierarchical chip planning, block planning , block level constraint development, hierarchical clock tree implementation, block integration and chip finishing.
• Multimode multi corner optimization and closure at top level.
• Clock tree synthesis and advanced clock tree implementation at full chip level.
• Top level timing closure with sign off STA in MMMC with cross-talk and OCV .
• Top level ECO implementation strategy development for netlist ,RTL and timing level changes
• Methodology development, customization as per the specific design need.
• Good hands-on knowledge in reference flows, excellent debugging skills.
• Scripting experience in Perl/TCL.
• Flow customization and fine tuning for Power , Performance, Area.
• Strong inter-personal skills and ability to work with multiple teams.
• In depth exposure in Implementation in any of the following platforms. • FC/ICC/Innovus; Tool exposure in Sign Off • DRC/LVS : Calibre • Timing sign off : Primetime • PNA : Apache -Redhawk Job Type: Full-time Experience: • Physical Design: 10-15 years