Computing System Architecture Engineer (Memory System Model and Optimization) (mediatek)
mediatek HsinChu, Taiwan(China)
2024-09-11
Job posting number: #150106 (Ref:MTK120240326006)
Job Description
Description
1. Memory subsystem (system cache, coherent interconnect, and memory controller) architecture design for Automotive or High-performance Computing2. System-level SW/HW behavioral power/performance analysis/optimization focusing on interplays between CPU/GPU/NPU/DSP/etc. and memory subsystem
3. Memory subsystem performance profiling and modeling
4. Memory subsystem competitive analysis
Requirements
Minimum qualifications:1. Master's degree in Electrical Engineering or Computer Science or equivalent practical experience
2. Experience using SystemC/Verilog/VHDL or C/C++/Python
3. Knowledge of system design and modeling tools
Preferred qualifications:
1. Experience with automotive-grade DRAM interface standards and memory technologies (DDR/LPDDR)
2. Familiarity with automotive safety/security standards such as ISO 26262 or ISO 21434.
3. Experience with design/optimization of memory hierarchy, coherence interconnect, shared system cache.