Senior DV manager (mediatek)
mediatek HsinChu, Taiwan(China)
2024-09-11
Job posting number: #150189 (Ref:MTK120231116000)
Job Description
Description
• Lead the DV effort of a high-end CPU project.• Manage, coach and guide DV engineers. Follow up status and keep up the schedule.
• Architect and implement top-module testbenches and their components using UVM-based methods.
• Lead the effort of building in-house BFMs to facilitate co-sim based module level verification.
• Architect and implement formal verification based module level testbench.
• Work with the design team to create testplans. Implement checkers/assertions/coverage check points.
• Work with validation folks to improve design visibility
View Orignal JOB on: italents.net
Requirements
• Masters/Bachelor or above degree in electronic/electrical engineering, computer science, mathematics or physics.• 15+ years of Verification experiences
• Solid experiences with SystemVerilog, UVM and etc.
• Experiences with major processor blocks.
• Good cross site and cross function execution skills