Top Integration Engineer (mediatek)
mediatek Hefei, China
2024-09-11
Job posting number: #150222 (Ref:MHF120240620000)
Job Description
Description
1. Responsible for Front-End Design Flow and other related ASIC TOP Integration work.2. SOC/Sub-System hierarchical architecture planning, design rule checking, including Synthesis, Equivalence Check, Timing Sign-off, Timing ECO, Low Power design rule check, performance/power/area quality boost, etc.
3. Support SOC physical implementation.
Requirements
JOB IS FROM: italents.netVIEW1. MSEE degree or above in microelectronics, computer, electronic engineering, communication engineering and other related fields2. Familiar with Verilog and ASIC front-end design flow, with solid digital circuit theory foundation, hands-on ability and innovation ability.
3. Professional in IC front-end EDA tools (such as DC/PT/LEC/VCS/DFTC/TMAX/Tessent platforms), and with ASIC design experience, such as: RTL coding, Synthesis, P&R, STA timing signoff, IR Analysis, etc.
4. Familiar with scripting language, such as Makefile/Tcl/Perl/Python, and etc.
5. Good communication and team-work skills, good English communication and presentation experience.
6. Passion work attitude, full of curiosity about technology, courage to take responsibility, and able to work under strong pressure.