SoC integration flow engineer (mediatek)
mediatek Taipei, Taiwan(China)
2024-09-11
Job posting number: #150314 (Ref:MTK120240524010)
Job Description
Description
1. SoC chip integration from RTL to gate level including timing closure and DFT2. Digital design methodology integration and QC flow improvement
Requirements
1. Cell base IC design flow knowledge and experience2. Digital IC design EDA tool and flow development experience
3. Basic RTL design experience and Timing/CTS/Physical concept
4. good script skill i.e. Per/Python/Tcl interested in programming
5. DFT knowledge and integration experience is plus