SOC Infra bus DV (mediatek)
mediatek Hefei, China
2024-09-11
Job posting number: #150370 (Ref:MHF120240620001)
Job Description
Description
1. Work closely with the Arch and design departments to ensure the completeness of the chip verification plan2. Responsible for the low power or Infra bus verification flow, and the setup and optimization of the verification platform
3. Plan the verification execution schedule according to the project milestone, track execution progress, and control risks
4. Responsible for the signoff of chip power feature verification or Infra bus verification
Requirements
Requirements:1. master’s degree in Microelectronics (ME), Computer Science (CS), Electronic Engineering (EE), Communication Engineering (CE), Automation (AU), or related fields
2. Strong responsibility and team collaboration spirit; excellent communication and execution skills; meticulous, responsible, and able to independently analyze and solve problems
3. Familiarity with System Verilog/VMM/UVM methodology
Preferred:
a) Familiarity with AMBA protocols and ARM-based SoC architecture
b) Familiarity with UPF/CPF and power-aware verification
c) Familiarity with scripting languages such as Python, Perl, or Tcl
d) Experience with successful SoC product tape out