[2025 Internship] Timing Signoff Engineer (CAI2/3) (mediatek)
mediatek Singapore, Singapore
2024-09-11
Job posting number: #149997 (Ref:MSL120230114010)
Job Description
Description
• Work on timing sign off, convergence, automations and methodology development.• Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
• Evaluate multiple timing methodologies/tools on different designs and technology nodes.
• Experience in design automation using TCL/Perl/Python
• Familiar with process technology enablement: Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.
• Strong expertise in STA timing analysis basics, AOCV/POCV/LVF concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
Requirements
• Bachelor's /Masters Degree in Electrical/Computer Engineering• Experience in ARM/IMG/Tensilica Processor Familiarity, Silicon Debug and/or Functional/Direct Test Verification
• Familiar with assertion based verification (SVA) & System Verilog language
• With knowledge in Processor verification, FPGA verification and/or Formal verification
• Familiar with Synopsys ICC (preferred) or Cadence or Magma tools from netlists to GDS is a must
• With knowledge in graphics processor implementation/power reduction flows and methodology from RTL to GDS (including synthesis, floor-planning, placement, CTS, routing, timing optimization, physical verification) is a plus
• Knowledge of high-speed/low power IP and custom circuit design is a plus
• Familiar with power noise and reliability tools such as Redhawk and Voltus
• Good communication and scripting skills
Are you the right talent? Send us your CV our way today! Kindly add "2024 SSIA / NTU & NTU-TUM Semiconductor awareness event" as a remark.