High speed interface IP design engineer_Taipei (mediatek)
mediatek Taipei, Taiwan(China)
2024-09-11
Job posting number: #150317 (Ref:MTK120240524008)
Job Description
Description
1. Die2Die digital PHY IP design, integration, including RTL integration, synthesis, MBIST, DFT, timing closure, test pattern generation, silicon debug, mass production issue resolving2. SOC chip integration from RTL to gate level including timing closure and testability
3. Design methodology and integration flow improvement
Requirements
1. Experienced in digital design flow.2. Familiar with UCIe specification is a plus.
3. Familiar with SOC IC IP/BUS integration, clock/reset structure.
4. Familiar with integration tools, ex.PrimeTime, Tweaker
5. Familiar with Perl, Python or TCL
6. Good problem resolving skill, willing to improve existing flow/methodology.